A hard drive is a non-volatile storage device that stores digitally encoded data on rotating platters with an associated magnetic surface. As shown in FIG. 1, a hard drive 100 includes a spindle 101 that holds at least one platter 102 having a magnetic surface 104, which spins at a constant speed (e.g., 10,000 revolutions per minute (rpm), 7,200 rpm, or 5,400 rpm). To write data onto a rotating platter, a portion of the magnetic surface 104 is magnetized via a magnetic write head 106. The write head 106 is coupled with an actuator arm 108 that moves radially across the spinning platters 102. To create a current pulse to control the write operation, a differential hard drive write system 110 including a hard drive controller 112 is coupled to the write head 106. The hard drive controller 112 is configured to control the read and/or write operations via a hard drive write system 110.
To increase hard drive write speed and capacity, the hard drive write system 110 generates narrow current pulses via a differential control pulse to write information to the magnetic surface 104. However, as the duration of the current pulse decreases to accommodate increased hard drive speed and storage capacity, the current pulse becomes distorted during transmission to the write head 106. To correct the distorted edge of the current pulse, the hard drive write system 110 produces current pulses with an overshoot portion to prevent distortion to the leading edge of the current pulse. The overshoot portion is followed by a sustain portion to write information to the platter for the full duration of the write operation.
FIG. 1B is a schematic illustration of a known prior art circuit that generates current pulses to drive the write head 106 in a hard drive write system 110. The example circuit includes two differential NAND 120 and 122 gates that perform the logic functions to create a pulse. The pulse is conveyed to a differential pair of transistors 130 and 132 to create a current pulse on the differential output. For the purpose of generating a current pulse, differential pair 130 is coupled to a first current source 140 and differential pair 132 is coupled to a second current source 142. The differential pairs 130 and 130 selectively couple their respective current source to either a write head 106 via an output or a low output signal such as a ground. For example, FIG. 1C illustrates an example output response from an example circuit of FIG. 1B.
To generate the current pulse, the differential pair 130 and 132 must uncouple the low output signal and couple the output within a fixed time period. Thus, if the switching rise time at the transistor bases does not occur between the time periods of T1-T2 or T3-T4 as illustrated in FIG. 1C, the example circuit fails to uncouple the low output signal and may not generate a current pulse to drive the write head 106. Additionally, the example circuit may only partially uncouple the low output signal and generate a portion of the current pulse. Thus, the example prior art circuit is sensitive to the rise time of the differential pair 130 and 132, which may result in pulse skipping as illustrated in FIG. 1D. Consequently, the NAND gates 120 and 122 exacerbate the performance of the example circuit by adding additional propagation delay associated with each NAND gate. To overcome the sensitivity to rise times, higher currents are applied to the circuit to slew capacitances of the differential NAND gates 120 and 122.